The integration of Group III-V semiconductors on a silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si-on-insulator (SOI), epitaxial transfer methods, epitaxial lateral overgrowth, selective epitaxy on patterned substrates, and aspect-ratio-trapping (ART) techniques have been investigated. However, significant levels of defects, high cost, and complex integration schemes have hampered large scale commercial impact.